The operation system with a floating point has been widely used in the work station for effecting scientific calculation and image processing, because this system has a wider dynamic range and a higher precision than the regular number arithmetic system. The FPU for use in the floating point arithmetic system is constituted by FPU which is called a co-processor having an interface with a given microprocessor for general use or by FPU which does not comprise an interface with respect to the microprocessor. The former FPU can be easily coupled with the microprocessor, but the operation speed is rather low in connection with the processing speed of the microprocessor. The latter FPU can operate at a speed higher than the former FPU by several tens times, so that its usability in the computer system of high operation speed is very high.
In case of using the high speed FPU, it is important how to construct the interface for connecting the FPU to the microprocessor serving as the host computer. For instance, the host computer, memory and FPU are connected to each other by providing address bus, data bus and bus-buffer for control line. The data transfer between the host computer and FPU is effected by means of the data bus of the host computer, and the data before the processing is loaded in RAM of FPU from memories of respective computers. The computers send commands for effecting the operation algorithm to FPU, and then the operation is initiated. After FPU has completed a single algorithm program, the host computer reads the result of operation out of an output RAM of FPU.
In the known operating system, the operation speed of the system is limited by the overhead time such as memory access due to the fact that the control instruction of the data transfer from the memory to FPU and the operating instruction are effected by the microcomputer, and therefore the high speed operation of FPU could not be sufficiently utilized. For instance, in case of executing the operation A=B+C, the following processes are required.
1 transfer of data B (memory.fwdarw.CPU.fwdarw.FPU) PA1 2 transfer of data C (memory.fwdarw.CPU.fwdarw.FPU) PA1 3 transfer of operating instruction PA1 4 operation PA1 5 transfer of operation result A (FPU43 CPU.fwdarw.memory)
In case of effecting this operation, the overhead time amounts to about 4 .mu.s, while the operation time itself is only 0.2 .mu.s, so that the high speed operation of FPU is not optimally utilized. Particularly, in case of effecting the vector operation by the repetitive operation with the aid of a loop of variable array, a very long time is required for calculating addresses of variables, so that the high speed processing of FPU could not be utilized efficiently.